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Senior Timing Methodology Expert
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As a Senior Staff Engineer in Timing Methodology, you will be responsible for leading the development of advanced timing closure flows and methodologies. You will work closely with cross-functional teams to design, develop, and implement cutting-edge solutions that meet the needs of our clients.
Required Skills and QualificationsWe are looking for individuals with thorough knowledge of the ASIC design cycle and timing closure flow and methodology. Candidates should have 10+ years of experience in timing constraints and timing closure, as well as expertise in STA tools such as Primetime, Tempus, and Tweaker. Strong understanding of advanced STA concepts and challenges in advanced nodes is also essential.
- Proficiency in scripting languages such as TCL, Perl, and Python
- Strong background in PNR and Extraction domain
- Experience with constraints development tools such as Spyglass
Candidates who are successful in this role will receive competitive compensation packages, comprehensive benefits, and opportunities for career growth and development.
OthersThe ideal candidate will possess leadership qualities to lead (technically) and manage the STA CAD team. A Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field, along with 6+ years of Hardware Engineering or related work experience, is required. Alternatively, a Master's degree in Computer Science, Electrical/Electronics Engineering, or related field, with 5+ years of Hardware Engineering or related work experience, may be considered. A PhD in Computer Science, Electrical/Electronics Engineering, or related field, with 4+ years of Hardware Engineering or related work experience, is also acceptable.
