Chief FPGA Designer

3 days ago


Bengaluru, Karnataka, India beBeeFpgaEngineer Full time ₹ 6,00,000 - ₹ 8,00,000

We are seeking a highly skilled FPGA Design Engineer to join our team. The ideal candidate will have expertise in developing FPGA solutions using VHDL or SystemVerilog, along with solid experience in hardware verification and debugging.

This role involves designing RTL for complex FPGA architectures, optimizing for performance and resource utilization, and ensuring robust verification and integration of your designs.

The successful candidate will design and implement high-quality RTL code for FPGA-based systems, primarily using VHDL or SystemVerilog. They will work on complex digital system designs, including signal processing, interface design, and integration of components such as memory controllers, processors, or peripheral devices.

Collaboration is key in this role, working closely with cross-functional teams including hardware engineers, firmware developers, and systems engineers to integrate and test complete FPGA solutions.

Responsibilities:

  • Design and develop FPGA solutions using VHDL or SystemVerilog
  • Develop digital system designs, including signal processing, interface design, and component integration
  • Work closely with cross-functional teams to integrate and test FPGA solutions
  • Create detailed design documentation, including specifications, schematics, test cases, and verification reports

Requirements:

  • 4+ years of hands-on experience in FPGA design and RTL development
  • Expertise in HDL design using VHDL or SystemVerilog
  • Strong understanding of digital logic design and FPGA architecture
  • Familiarity with FPGA toolchains like Xilinx Vivado, Intel Quartus, or Lattice Diamond
  • Experience with FPGA verification using simulation tools such as ModelSim, VCS, or Questa

Preferred qualifications include experience with scripting languages (e.g., TCL, Python) for automation and tool integration, as well as knowledge of timing analysis, clock domain crossing, and resource optimization techniques in FPGA design.


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