Capgemini Verification Engineer

2 weeks ago


Anywhere in IndiaMultiple LocationsBangaloreHyderabad capgemini Full time

**Verification Role Overview**

We are seeking a highly skilled Design Verification Engineer - System Verilog to join our team at Capgemini. The ideal candidate will be responsible for verifying IPs and SoCs leading to first Si success.

Key Responsibilities:

  • Manage and lead a team of Verification engineers
  • Develop efficient test benches and test cases using the latest industry standard methodologies and HVLs
  • Define verification strategy, write test plans, and ensure code coverage, functional coverage, and assertions are met
  • Work on ARM based SoC verification and have experience with GLS
  • Proficiency in one scripting language like Perl, C++, Python, Unix Make, or Unix Shell Scripts is a great plus

Primary Skills:

  • Verilog, SV, UVM/OVM, IP Verification, SoC Verification, scripting - Perl, Python, Shell, and Tcl

Secondary Skills:

  • Test bench / model / VIP development, Functional coverage, GLS, LEC, Emulation, AMS, ARM, Protocols AHB/AXI/APB, Ethernet, USB, PCIe, I2C, SPI, CAN, Mipi CSI/DSI, LPDDR


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