
Digital Verification Specialist
2 weeks ago
We are seeking an experienced Verification Engineer to lead our digital verification process. This role involves developing and executing comprehensive verification plans using Verilog/SystemVerilog and SDF concepts.
- This includes collaborating with cross-functional teams to identify and resolve design issues during the verification phase.
- The successful candidate will utilize EDA tools such as Synopsys VCS, Cadence Xcelium, and Mentor Questa to ensure efficient and accurate verification.
- Prior experience in timing analysis, synthesis, and place & route (PnR) flow is essential for this position.
- X-checking, reset verification, and glitch detection techniques in gate-level simulation are also key skills required.
- A strong understanding of scripting languages such as Perl, Python, TCL, and Shell is necessary for success in this role.
- Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering or equivalent.
- 4+ years of experience in digital verification, with a focus on GLS.
- Strong knowledge of Verilog/SystemVerilog, and SDF concepts.
- Familiarity with EDA tools such as Synopsys VCS, Cadence Xcelium, Mentor Questa, etc.
- Excellent debugging and problem-solving skills.
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