
Advanced Memory Design Expert
1 week ago
Job Overview
We are seeking a seasoned Memory Design Engineer to fill a critical role in our organization. The ideal candidate will possess a strong background in full custom Memory design & architectures, with hands-on experience in characterization, layout design, net-listers, and complete SRAM Design verification at compiler level.
Key Responsibilities
- Develop and publish strategic project plans, ensuring timely completion and quality deliverables.
- Design and optimize physical layouts for memory cells, arrays, and peripheral circuits using industry-leading tools like Cadence Virtuoso or Synopsys Custom Compiler.
- Expertise in working on memory layout design for advanced nodes (TSMC: 7nm/5nm/3nm).
- Proficient in various physical verification flow debug, like DRC, LVS, DFM, PERC, ERC, EM, IR.
- Excellent understanding of good layout practices in lower process nodes like 7nm and 5nm.
- Expertise working on FinFET architecture and challenges such as variability and manufacturability.
- Minimum 8 years of experience required.
Requirements
- Strong knowledge of different types of Memory architecture.
- Hands-on experience on SRAM leafcell GDS from scratch till top-level integration.
- Proficient in Cadence Virtuoso layout editor and Caliber Physical verification flow.
- Synopsys Custom Compiler experience is highly desirable.
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