Senior Verification Expert
5 days ago
**Job Summary:** We are seeking a seasoned verification engineer to lead the design verification process for complex System-on-Chip (SoC) designs. The ideal candidate will have extensive experience in designing and implementing high-quality verification plans, testbenches, and constrained-random tests.
Key Responsibilities:
- Design and implement verification plans, testbenches, and constrained-random tests for SoC designs.
- Lead a team of engineers in the development and execution of verification plans.
- Collaborate with cross-functional teams to identify and address verification challenges.
- Develop and maintain expertise in industry-leading EDA tools and methodologies.
- Stay up-to-date with emerging trends and technologies in the field of digital design and verification.
Required Skills and Qualifications:
- Bachelor's degree in Computer Science, Electrical Engineering, or related field.
- 5+ years of hands-on experience in digital design and verification, with a focus on System Verilog and UVM.
- Proven track record of leading a team of engineers in the development and execution of verification plans.
- Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM.
- Experience in using EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper.
- Experience in using revision control systems such as Git, Perforce, Clearcase.
- Desirable skills include SVA and formal verification, as well as scripting languages such as Python, Perl, or TCL.
Benefits:
- Competitive salary and benefits package.
- Ongoing training and professional development opportunities.
- Collaborative and dynamic work environment.
Others: If you are a motivated and experienced verification engineer looking to take your career to the next level, we encourage you to apply. Please submit your resume and a cover letter outlining your relevant experience and qualifications.
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