VLSI Design and Optimization Specialist

16 hours ago

Bengaluru, Karnataka, India beBeeCAD Full time ₹ 1,04,000 - ₹ 1,30,878
Job Overview

The role of Static Timing Analysis CAD Engineer involves developing, maintaining and optimizing static timing analysis flows and methodologies with a focus on Synopsys PrimeTime. This position requires expertise in static timing analysis, CAD flow development, and proficiency in TCL, Perl and Python scripting for automation.

Key Responsibilities:

  • Develop, support and optimize STA CAD flows and methodologies using Synopsys PrimeTime for VLSI designs.
  • Collaborate with design and implementation teams to establish timing constraints and ensure timing closure.
  • Develop scripts and automation solutions using TCL, Perl and Python for timing analysis, report generation and optimization.
  • Work closely with physical design and verification teams to ensure timing requirements are met across multiple process, voltage and temperature corners.
  • Generate detailed timing reports, identify and resolve timing violations and implement optimizations.
  • Evaluate and implement new EDA tools and methodologies to improve STA efficiency and accuracy.

Requirements:

  • Bachelor s or Master s degree in Electrical Engineering, VLSI or a related field.
  • Minimum of 5+ years of relevant experience in static timing analysis, CAD flow development and Synopsys PrimeTime.
  • Proficiency in TCL, Perl and Python scripting is necessary for CAD automation and customization.
  • Familiarity with advanced technology nodes e.g. 7nm, 5nm and timing constraints in complex designs.
  • Strong understanding of timing closure methodologies and STA best practices

Technical Expertise:

  • TCL, Perl and Python scripting
  • Synopsys PrimeTime
  • STA CAD flows and methodologies
  • VLSI designs
  • Timing constraints and timing closure

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