Senior Digital Design Engineer

2 weeks ago

Bengaluru, Karnataka, India Analog Devices Full time

Job Summary:

We are seeking a highly skilled Senior Digital Design Engineer to join our team at Analog Devices. As a key member of our design team, you will be responsible for developing detailed specifications, designing digital blocks, and leading small teams of micro-architects and RTL developers.

Key Responsibilities:

  • Develop detailed specifications and design digital blocks such as accelerators and datapath IP in Verilog and SystemVerilog.
  • Work closely with the architecture team to develop detailed specification, uArch, and development plans.
  • Design key digital blocks such as accelerators and datapath IP in Verilog and SystemVerilog with built-in configurability to allow power, performance, and area tradeoffs.
  • Develop a strong understanding of heterogeneous processor cores and subsystems, including ARM, RISC-V, and DSP cores, and their integration requirements.
  • Develop user guides for RTL integration, synthesis, lint/CDC waivers, DFT, PnR, programming sequence, characterization, and other related tasks.
  • Evaluate third-party IPs on power, performance, and area, and other key qualitative aspects such as design quality, design for testability, and robustness of design verification practice.
  • Provide technical leadership and guidance to small teams of micro-architects and RTL developers working on an SoC.
  • Work closely with the verification team for vPlan reviews and for complex debugs to resolve verification failures.
  • Participate in design specification, micro-architecture, and verification sign-off reviews.
  • Improve flows and methodologies to streamline IP development and integration.
  • Build development teams, including recruiting and interviewing.

Requirements:

  • Minimum B.E./B.Tech degree in Electrical/Electronics/Computer Science.
  • 5-8 years of digital logic design and hands-on RTL coding experience using Verilog and SystemVerilog.
  • Strong understanding of control path and data-path digital design concepts with an eye for realizing correct-by-construction solutions.
  • Experience with specifying design verification requirements such as test plans, coverage metrics, and evaluating DV quality to realize robust design quality.
  • Knowledge of lint, CDC, formal equivalence, DFT concepts, power analysis, and other related tasks.
  • Experience with developing timing constraints and ability to carry out logic synthesis and static timing analysis.
  • Good interpersonal, teamwork, and communication skills to logically and effectively drive discussions with teams spread geographically.
  • Understanding of standard on-chip interfaces such as APB/AHB/AXI/Stream protocols is a strong plus.
  • Knowledge of processor/SoC architecture and/or DSP fundamentals is a strong plus.
  • Experience with end-to-end ASIC/SoC product development and productization is very desirable.

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