Digital Fault Analysis Expert

3 weeks ago


Bengaluru, Karnataka, India Tata Consultancy Services Full time

Seeking a highly skilled Digital Fault Analysis Expert to join our team at Tata Consultancy Services. The ideal candidate will have experience in Chip Level DFT and Post Silicon debug/analysis, with a strong understanding of DFT architectures such as scan chain insertion and verification, scan compression techniques, and JTAG.

Key Responsibilities:

  • ATPG pattern generation
  • ATPG coverage analysis
  • Pattern simulation (both timing/no timing)
  • Pattern retargeting
  • Understanding JTAG/IJTAG
  • MBIST and Logic BIST

Requirements:

  • Proficient in writing SDC constructs for DFT modes
  • Proficient in Python, PERL/Shell script
  • Excellent hands-on debug skills and problem-solving attitude
  • Strong digital design concepts
  • Generating scan patterns and coverage statistics for various fault models such as stuck at, IDDQ, transition faults, JTAG BSDL, and pattern generation for memories (E-fuse etc.)


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