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Senior Verification Expert

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Job Title: Senior Verification Expert

We are seeking an experienced Senior Verification Expert to lead our design verification efforts.

  1. ">
  2. System Verilog and UVM (Universal Verification Methodology): Proven experience in developing verification environments, creating testbenches, and writing functional coverage.
  3. C Programming: Strong coding skills in C for unit, subsystem, and SOC level verification.
  4. RTL Simulations: Experience with Synopsys and Cadence simulators for performing RTL simulations.
  5. Power Aware Simulations: Knowledge of UPF (Unified Power Format) based power aware simulations.
  6. Assertion and Functional Coverage: Skilled in coding assertion and functional coverage bins in SVA (System Verilog Assertions).

Responsibilities:

  • Developing verification environment architecture documents.
  • Reviewing and revising working towards meeting agreed upon acceptance criteria.
  • Performing gate-level simulations.
  • Preparing and conducting reviews of verification sign-off documents to ensure SOC tape-out quality.

Benefits:

  • Opportunity to work with cutting-edge technologies.
  • Collaborative and dynamic work environment.
  • Competitive compensation and benefits package.

Requirements:

  • 7+ years of experience in design verification.
  • Mastery of System Verilog, UVM, C programming, and RTL simulations.
  • Strong problem-solving skills and attention to detail.