Design Verification Specialist
1 week ago
Job Title: Design Verification Specialist
Job Description:
We are seeking a skilled Design Verification Specialist to join our team at Maneva Consulting Pvt. Ltd. The successful candidate will be responsible for creating and reviewing verification environment architecture documents, developing code in System Verilog UVM and C, and performing RTL simulations using Synopsys and Cadence simulators.
Key Responsibilities:
- Understanding business requirements and functional specifications of IPs
- Creating verification environment architecture documents
- Reviewing and revising documents to meet acceptance criteria
- Developing code in System Verilog UVM and C for unit and SOC level verification
- Performing RTL simulations using Synopsys and Cadence simulators
- Debugging and resolving problems found by simulations
- Developing performance test plans and maintaining them
- Implementing performance verification flow, including monitoring, synchronization, reporting, and self-checking mechanisms
- Providing full reports of performance metrics and bottlenecks
- Tracking tickets and code releases using Bug Tracking tool and GIT
- Performing UPF-based Power Aware simulations
- Coding assertions and functional coverage bins in SVA
- Performing gate level simulations
- Preparing and conducting reviews of verification signoff documents to ensure SOC tapeout quality
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