Senior ASIC Design Engineer

7 days ago


Bengaluru, Karnataka, India Syntiant Corp. Full time
Job Description

We are seeking an experienced and talented Sr. ASIC Design Engineer to join our team at Syntiant Corp., a leader in delivering hardware and software solutions for edge AI deployment.

The ideal candidate will be responsible for developing Syntiant's next-generation Neural Decision Processor SoCs. This role requires a self-starter who can execute all design cycle tasks from architecture to tapeout, as well as silicon bring-up and validation while working with cross-disciplinary teams (Design, Firmware, Product, OPS & Field Engineering).

About the Role

This is a unique opportunity to work on cutting-edge projects and contribute to the development of ultra-low-power, high-performance deep neural network processors.

You will be part of a dynamic team that values innovation, collaboration, and continuous learning.

Responsibilities
  • Microarchitecture and implementation of SoC design blocks
  • Integrate and verify design blocks at chip level
  • Quality checks of implemented RTL with LINT, CDC, and DFT rules, with clear documentation of exceptions and waivers
  • Synthesis, constraints, and timing closure for the SoC
  • Logic Equivalence Check (LEC) for SoC design blocks and for the full SoC
  • Implement low power modes for the SoC using UPF
  • Implement Design-for-Test (DFT) features in the SoC
  • Participate in silicon bring-up, validation, and characterization
  • Provide quality documentation of the implementation and other deliverables with systematic reviews
Requirements

To be successful in this role, you will need:

  • An advanced degree in Electrical Engineering or Computer Engineering
  • A track record of 'first-pass success' in ASIC development cycles
  • 6+ years of experience with SoC development using SystemVerilog/SystemC
  • Expertise in SoC and Subsystem design of ARM-based SoCs
  • Deep understanding of Synthesis, constraint development, and timing closure
  • Deep understanding of design quality checks (Lint, CDC, DFT rules)
  • Experience with Low Power Design using UPF
  • Experience with scripting languages, e.g. Python
  • Experience with High Level Synthesis (HLS) using SystemC is a big plus
  • Experience with silicon bring-up and debug as well as developing chip demo
  • Experience with SoC performance analysis is a plus
  • Knowledge of ARM architecture and AMBA bus standards like AXI, AHB & APB
  • Knowledge of Design for Test (DFT) features and implementation is a plus
  • Knowledge of SoC power estimation flow is a plus
Salary Range

We offer a competitive salary range of $140,000 - $180,000 per year, depending on experience, location, and qualifications.

This estimate is based on national averages and may vary depending on individual circumstances.



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