High Performance ASIC Engineer Required
23 hours ago
We seek an accomplished engineering leader to drive exceptional results in ASIC solutions.
The ideal candidate will have a proven track record in optimizing physical design to deliver industry-leading performance, power efficiency, and area reduction.
- Develop RTL to GDS2 flow strategies
- Manage floor-planning, physical implementation of power planning, synthesis, placement, CTS, timing closure, routing, extraction, DRC & LVS, crosstalk analysis, EM/IR, formal equivalence verification
- Be proficient in handling PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus
Key Responsibilities:
- Full Chip Level Floor Planning, Bus / Pin Planning, Feed-Through Planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification, and Sign Off
- Identify complex technical problems, break them down, summarize multiple possible solutions
- Drive hands-on flow development and scripting
PREFERRED EXPERIENCE:
- 12+ years of professional experience in physical design, preferably with high-performance designs
- Experience in automated synthesis and timing-driven place and route of RTL blocks for high-speed datapath and control logic applications
- Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction
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