
Verification Engineering Specialist
2 days ago
We are seeking a skilled Verification Engineering Specialist to lead our design verification teams.
- Main Responsibilities:
- Leverage expertise in UVM and System Verilog coding to develop functional verification plans.
- Collaborate with cross-functional teams to identify and address technical issues.
- Maintain strong knowledge of verification environment development, resource allocation, and process improvement strategies.
About the Ideal Candidate:
- Must have a degree in Electrical / Electronics / VLSI engineering or related field.
- Minimum 5 years of experience in design verification, with expertise in SV/UVM.
- Proven track record of leading successful verification projects from concept to closure.
- Familiarity with IP verification of memory IP (DDR/HBM/GDDR) is an added advantage.
What We Offer:
- A collaborative work environment that fosters professional growth.
- Competitive salary and benefits package.
Key Skills:
- UVM and System Verilog coding.
- Functional verification environment development.
- Process improvement strategies.
- Resource allocation.
- IP verification of memory IP.
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