
Advanced ASIC Design Specialist
13 hours ago
This is a challenging role for an experienced Senior Physical Design Engineer. The successful candidate will be responsible for the entire physical design flow, from floor planning to tapeout.
Responsibilities:- Top-level floor planning, placement and routing, scan-chain-reordering, clock tree synthesis, timing optimization, signal integrity aware routing, timing analysis/closure, and engineering change order (ECO) tasks.
- Worked on advanced low power designs with techniques such as voltage islands, power gating, and substrate bias.
- Provide technical guidance and mentoring to junior engineers.
- Interface with front-end ASIC teams to resolve issues.
- Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques.
- Timing closure on DDR2/DDR3/PCIE interfaces.
- Excellent communication skills.
- Strong background of ASIC Physical Design: Floor planning, Placement & Routing, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
- Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.
- Expertise in scripting languages such as PERL, TCL.
- Strong Physical Verification skill set.
- Static Timing Analysis in Primetime or Primetime-SI.
- Good written and oral communication skills. Ability to clearly document plans.
- Ability to interface with different teams and prioritize work based on project needs.
Requirements:
• 3 to 12 Years of Experience in Physical Design Engineering
Location:
Hyderabad
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