Static Timing Optimization Expert

4 days ago


Madurai, Tamil Nadu, India beBeeSkills Full time ₹ 2,00,00,000 - ₹ 2,50,00,000
Static Timing Analyst

Our team is seeking a highly skilled Static Timing Analyst to lead STA and Place and Route activities for complex subsystems. The ideal candidate will have expertise in STA tools, PNR tools, and scripting languages.

This role requires a strong understanding of SoC design flows, with experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems.

The successful candidate will have a proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.

They will be proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks.

Additionally, they will have experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level.

Key Qualifications:
  • 10+ years of experience in Static Timing Analysis (STA) and Place and Route (PNR) for complex subsystems within ASIC/SoC design, including advanced technology nodes (7nm, or below).
  • Demonstrated expertise in STA tools (e.g., Synopsys PrimeTime, Cadence Tempus) and PNR tools (e.g., Synopsys ICC2, Cadence Innovus) applied to large, multi-block or hierarchical subsystems.
  • Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.
  • Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks.
  • Deep understanding of SoC design flows, with experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems.


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