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Senior ASIC Verification Professional
2 weeks ago
We are seeking a skilled Verification Engineer to join our team. As a key member of our verification team, you will be responsible for developing and implementing verification plans, environments, and test benches.
Key Responsibilities:- Develop and implement verification plans, environments, and test benches to ensure the functionality and quality of our designs.
- Evaluate and exercise various aspects of the development flow, including Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics.
- Collaborate with architects, designers, VIP team, and peers to accomplish all verification goals.
- Identify design problems, possible corrective actions, and/or inconsistencies on documented functionality.
- Adhere to quality standards and good test and verification practices.
- Proven desire to learn and explore new state-of-the-art technologies.
- Demonstrate good written and spoken English communication skills.
- Demonstrate good review and problem-solving skills.
- Knowledgeable with Verilog, VHDL, and/or SystemVerilog.
- Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus.
- Understanding of verification methodology such as UVM.
- Good organization and communication skills.
- 5+ years of relevant experience.
