Physical Layout Expert
1 day ago
Job Overview
Askexim Services (P) Limited is seeking a highly skilled Physical Design Engineer to join our team. The successful candidate will contribute to the design and development of high-performance integrated circuits from RTL to delivery of final GDSII.
About the Role
- Generate block/chip level static timing constraints
- Build a full chip floor plan including pin placement, partitions, and power grid
- Develop and validate high-performance low-power clock network guidelines
- Perform block-level place and route and close the design to meet timing, area, and power constraints
- Generate and implement ECOs to fix timing, noise, and EM IR violations
- Run Physical design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers
- Participate in establishing CAD and physical design methodologies for correct construction designs
- Assist in flow development for chip integration
Requirements
- Bachelor's/Master's degree in Electrical Engineering, Computer Engineering, or related field
- Deep knowledge of industry standards and practices in Physical Design, including Physical aware synthesis, Floor-planning, and Place & Route
- Experience in developing and implementing Power-grid and Clock specifications
- Strong understanding of all aspects of Physical construction, Integration, and Physical Verification Shown
- Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic design team for timing fixes Power user of industry standard Physical Design & Synthesis tools
- Deep understanding of scripting languages such as Perl/Tcl, solid understanding of Extraction and STA methodology and tools
- Deep understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level
What We Offer
- A competitive salary of $140,000 - $200,000 per annum
- A comprehensive benefits package
- The opportunity to work on high-profile projects and collaborate with experienced professionals
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