
Senior RTL Principal Design Engineer Opportunity
2 weeks ago
As a Senior Engineering Lead, you will be responsible for driving the development of our cutting-edge Interface Controller IP solutions. This role is based in India and requires expertise in RTL design and support for PCIe/CXL/IDE/UALink IP solutions.
Key Responsibilities:
- Lead the design and support of RTL for interface controller IP development teams
- Collaborate with cross-functional teams to ensure clean and efficient designs
- Develop and implement new features, ensuring compliance with LINT and CDC design guidelines
- Support customers and ensure smooth verification regressions
- Work with existing RTL, adding new features and maintaining customer configurations
Requirements:
- Bachelor's degree in Electrical / Electronics / VLSI engineering or equivalent experience
- 8-16 years of core RTL design experience using Verilog
- System Verilog experience and UVM-based environment usage/debugging
- PCIe/CXL/IDE experience, with prior implementation of complex protocols
- Prior experience in IP development teams is an added advantage
- Opportunity to work on cutting-edge technologies
- Chance to lead and mentor high-performing teams
- Competitive salary and benefits package
- Ongoing training and development opportunities
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