
Senior Verification Project Lead
2 days ago
As a Verification Manager, you will be responsible for leading end-to-end technical leadership and project execution in the Design Verification domain. You will define verification strategies, test plans, coverage goals, and closure metrics aligned with our standards.
Key Responsibilities:
- Lead technical teams to drive seamless execution across global sites.
- Collaborate with architects, designers, and engineers to deliver high-quality designs.
- Provide guidance on SystemVerilog, UVM-based testbench development, coverage closure, debugging, and verification methodologies.
- Manage DV teams, track progress, and mitigate risks through proactive planning.
- Conduct status reporting, milestone reviews, and client interactions.
- Mentor junior engineers and ensure adherence to best practices in verification and project management.
Required Skills & Experience:
- 14 to 20+ years of experience in Design Verification (IP / Subsystem / SoC level).
- Strong expertise in SystemVerilog, UVM, SVA, and coverage-driven verification.
- Hands-on knowledge of AMBA protocols (AXI, AHB, APB) and Memory/DRAM verification flows.
- Experience with Gate Level Simulation (GLS), Low Power (UPF), and Formal Verification is a strong plus.
- Exposure to EDA tools such as Cadence Xcelium, Synopsys VCS, and Verdi.
- Proven experience in project/program management, leading DV teams (10+ engineers).
- Strong stakeholder management, planning, and execution skills.
Benefits
- Opportunity to work on cutting-edge memory and SoC verification projects.
- Lead high-impact DV programs with global exposure.
- Collaborate with a technically strong, innovative team.
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