Senior DFT Design Engineer

10 hours ago

Salem, Tamil Nadu, India beBeeDft Full time ₹ 22,00,000 - ₹ 25,50,000

Job Title: Senior DFT Design Engineer

We are seeking an experienced Senior DFT Design Engineer to drive the design and implementation of digital test strategies for complex SoC/ASIC designs.

The ideal candidate will have a strong background in DFT, with expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.

A key responsibility will be to develop and maintain DFT automation scripts and infrastructure, as well as mentor junior engineers and conduct design reviews.

The successful candidate will have 7+ years of experience in DFT for complex ASIC or SoC designs, with a strong understanding of RTL design, STA, and synthesis flows.

They will also be proficient in scripting languages (Python, Perl, Tcl) and have a deep understanding of silicon test challenges and test coverage improvement.

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design is required.

The role offers competitive salary, leadership exposure, and fast-track growth opportunities, working with top-tier engineers and global semiconductor leaders on high-performance, next-gen SoCs and ASICs.

  • Key Responsibilities:
    • DFT Strategy and Architecture: Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.
    • DFT Implementation and Verification: Lead implementation and verification of DFT features like scan insertion and compression, ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan (IEEE 1149.1/1149.6), and IJTAG (1687).
    • End-to-End DFT Flow Management: Manage end-to-end DFT flow from RTL to gate-level netlist and silicon bring-up.
    • Collaboration and Mentorship: Collaborate with RTL, STA, PD, and test engineering teams for seamless integration, mentor junior DFT engineers, conduct design reviews, and training sessions.
    • DFT Automation and Scripting: Develop and maintain DFT automation scripts and infrastructure.

Required Skills and Qualifications:

  • Education: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.
  • Experience: 7+ years of experience in DFT for complex ASIC or SoC designs.
  • Expertise: Scan insertion, compression, ATPG, MBIST, and boundary scan.
  • Tools: Synopsys: DFT Compiler, TetraMAX, TestMAX; Siemens EDA: Tessent ScanPro, MBIST, IJTAG; Cadence/others: Modus, Encounter Test.
  • Languages: Python, Perl, Tcl.
  • Synthesis Flows: RTL design, STA, and synthesis flows.
  • Leadership and Collaboration: Strong leadership, team collaboration, and communication skills.

Benefits:

  • Competitive Salary: Competitive salary package.
  • Leadership Exposure: Opportunities for leadership growth and development.
  • Fast-Track Growth Opportunities: Fast-track career advancement opportunities.
  • Collaborative Environment: Collaborative and innovative work environment.

Other Opportunities:

  • Professional Development: Opportunities for professional growth and development.
  • Global Network: Global network of top-tier engineers and semiconductor leaders.

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