Distinguished Chip Architect

We are seeking a highly skilled Physical Design Engineer to join our team.

The successful candidate will be responsible for designing and implementing complex digital circuits using advanced EDA tools. Experience in floorplanning, placement, budgeting, clock tree planning & analysis, scan re-ordering, clock tree synthesis, placement optimizations, routing, timing, and SI analysis/closure is essential.

Key responsibilities:

• Develop and implement physical design methodologies for full-chip and block-level designs.
• Collaborate with the methodology team to improve design automation tools and flow.
• Work closely with cross-functional teams to ensure timely delivery of high-quality designs.
• Ensure compliance with industry standards and regulations.

Requirements:

• 4+ years experience in ASIC physical design.
• Strong communication and problem-solving skills.
• Experience with block implementation, extraction, timing, and or full-chip designs.

Preferred qualifications:

• Experience as a full-chip floorplanning, routing, or timing lead for a large silicon project.
• Track record of taping out complex chips on advanced process nodes.

We offer a competitive salary and benefits package, as well as opportunities for career growth and professional development.