GPU Architectural Designer

3 days ago

Greater Hyderabad Area, India beBeeEngineer Full time ₹ 2,00,00,000 - ₹ 2,50,00,000
Senior Design Engineer for High-Performance GPU Architecture

We are seeking an experienced design engineer to lead the development of high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration solutions for GPUs.

Key Responsibilities:
  • Design IP blocks for GPU cores, including systolic arrays, vector units, and memory subsystems.
  • Develop Verilog/SystemVerilog RTL for performance, timing, and area optimization.
  • Implement high-speed interconnects (e.g., AXI, NoC) for GPU data pipelines.
  • Optimize designs for high throughput, low latency, and power efficiency in AI workloads.
  • Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces.
  • Support synthesis, timing closure, and FPGA prototyping and design verification team.
Requirements
  • Education: BS/MS in Electrical/Computer Engineering.
  • Experience: 10+ years in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or GPU-like architectures.
  • Skills:
    • Proficient in Verilog/SystemVerilog RTL design.
    • Knowledge of GPU architectures, systolic arrays, or matrix multiplication units.
    • Experience with AXI, NoC, or similar interconnect protocols.
    • Familiarity with LPDDR6, HBM3, DDR5, or high-bandwidth memory interfaces.
    • Proficiency with synthesis and timing tools (e.g., Synopsys Design Compiler).
    • Strong problem-solving and teamwork skills.
Preferred Qualifications
  • Experience with AI/ML workloads or datacenter designs and GPU architectures.
  • Knowledge of CXL, PCIe, UALink, or Ultra Ethernet.
  • Familiarity with power optimization for high-performance chips.
What We Offer:
  • Pure play product work environment.
  • Chance to work with a tightly knit group of exceptional engineers who come from top companies.
  • A meritocracy first work place where each peer is a star.
  • A chance to be part of industry shaping product in entirety from initial stages.
  • A chance to learn from industry veterans who have already launched multiple billion-dollar semiconductor firms over the last three decades.

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