
Leading RTL Principal Design Engineer Position
23 hours ago
- Design and support the RTL of interface controller IP solutions.
- Based in Bangalore or Noida, this role involves working with existing RTL code, adding new features, ensuring customer configurations are clean for verification regressions, and supporting customers.
- The ideal candidate will have experience in core RTL design using Verilog, system verilog, and UVM based environment usage/debugging.
- Prior experience in implementation of complex protocols is a must, especially PCIe/CXL/IDE. Experience in IP development teams would be beneficial.
- A Bachelor's degree or higher in Electrical/Electronics/VLSI engineering, with 8-16 years of experience as a design and verification engineer, is required.
Required Skills:
- Bachelor's degree in Electrical/Electronics/VLSI engineering
- 8-16 years of experience as a design and verification engineer
- Core RTL design experience using Verilog
- System Verilog experience and UVM based environment usage/debugging
- PCIe/CXL/IDE experience and prior experience in implementation of complex protocols
- IP development team experience an advantage
- Scripting knowledge advantageous
Benefits:
This position offers a unique opportunity to work on cutting-edge technology, collaborate with experienced professionals, and enhance your skills in RTL design and verification.
Other Requirements:
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