
Senior ASIC Physical Designer
1 day ago
We are seeking a skilled Physical Design Engineer to join our team. The successful candidate will be responsible for all aspects of physical design, including floorplanning, placement, budgeting, clock tree planning and analysis, scan reordering, clock tree synthesis, placement optimizations, routing, timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, low power solution development & implementation.
The ideal candidate will have sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools & flow, etc.
You will work closely with the methodology team to solve implementation challenges and provide inputs to improve the physical design flow.
Required Skills and Qualifications:- 4+ years experience in ASIC physical design
- Experience with block implementation, extraction, timing and/or full-chip designs
- Strong communication skills
- Strong hands-on TCL/Perl development skills
- Experience as a full-chip floorplanning, routing, or timing lead for a large silicon project
- Track record of taping out complex chips on advanced process nodes
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