Senior Chip Design Specialist

6 days ago


Gandhinagar, India beBeeAnalogLayoutEngineer Full time

Job TitleWe are seeking a highly experienced Analog Layout Engineer with strong expertise in chip-level handling of high-speed analog IPs.Perform complete analog layout design including floorplanning, routing, matching, shielding, EM/IR checks, and parasitic optimization.Run post-layout simulations (extracted netlist, corners, Monte Carlo) and ensure correlation with schematic.Lead IP verification, including DRC, LVS, ERC, ANT, PEX, and reliability checks.Key ResponsibilitiesHandle chip-level planning and integration of high-speed analog IPs.Drive complete IP signoff ownership, ensuring zero violations at final GDS delivery.Work closely with foundry teams for:Clarifications on PDK and LVS/DRC rule updates.Model issues and PEX rule discussions.Tape-out requirements and signoff guidelines.Requirements8+ years of solid experience in Analog/Mixed-Signal Layout.Deep expertise in high-speed IPs (SERDES, PLL, ADC/DAC, Tx/Rx, clocking blocks).Strong understanding of chip-level integration, hierarchy, and physical interfaces.Preferred SkillsExperience working with advanced nodes (5nm).Exposure to SERDES / PCIe / MIPI / USB high-speed IPs.Experience coordinating with global customers.



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