STA Engineers
1 week ago
Static Timing Analysis (STA) Engineer Job Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and physical design teams to achieve the target operating frequency and performance metrics. Key Responsibilities Timing Sign-off and Analysis Timing Closure Ownership: Drive all aspects of timing closure from pre-layout to post-layout for blocks, sub-systems, and/or the full chip. Constraint Management: Develop, validate, and maintain Synopsys Design Constraints (SDC) and timing constraints for all functional and test modes (e.g., Scan, MBIST). MMMC Analysis: Perform comprehensive timing analysis across multiple operating corners (Process, Voltage, Temperature - PVT) and various modes (Multi-Mode Multi-Corner). Critical Path Identification: Analyze timing reports to identify and debug critical paths and resolve all Setup and Hold violations. Signal Integrity (SI) & Noise: Incorporate advanced timing effects such as on-chip variation (OCV), signal integrity (crosstalk), and voltage drop (IR-drop aware STA) into the sign-off process. Methodology and Flow Develop, maintain, and enhance STA flows and methodologies to improve efficiency, robustness, and reduce analysis runtime. Automate repetitive tasks and report generation using scripting languages. Generate final timing reports and sign-off collateral for tape-out. Education Bachelor's or Master's degree in Electrical Engineering (EE), Electronics Engineering, VLSI, or a related field. Technical Skills & Experience Experience: 3+ years of experience in STA. EDA Tools: Expert proficiency with industry-standard Electronic Design Automation (EDA) tools from vendors like Synopsys (e.g., Fusion Compiler, ICC2, Primetime), Cadence (e.g., Innovus), or Mentor Graphics. Soft Skills Excellent analytical, debugging, and problem-solving skills. Strong verbal and written communication skills. Ability to work effectively in a team environment and collaborate across different engineering disciplines. Experience Level :- 3yrs to 15yrs Notice Period :- Immediate to 60 Days Work Location :- Bangalore Mode of Work :- WFO Employment Type :- Permanent
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STA Engineer
1 week ago
bangalore district, India ACL Digital Full timeJob Title: STA Engineer Location: Banglaore/Hyderabad Employment Type: Full-time Industry: Semiconductors / VLSI / ASIC Design Job Summary: We are looking for a skilled and motivated STA Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting...
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STA Engineer
1 week ago
bangalore district, India Sintegra Inc. Full timeJob Summary: We are seeking a skilled STA Engineer with a strong background in Test and DFT architectures. The ideal candidate will have hands-on experience evaluating and writing high-quality timing constraints (SDCs) and performing thorough timing checks across complex digital designs. Key Responsibilities: Analyze and validate timing constraints (SDC) for...
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STA Engineer
1 week ago
Bangalore, India ACL Digital Full timeJob Title: STA Engineer Location: Banglaore/Hyderabad Employment Type: Full-time Industry: Semiconductors / VLSI / ASIC Design Job Summary: We are looking for a skilled and motivated STA Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting...
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STA Engineer
1 week ago
bangalore, India ACL Digital Full timeJob Title: STA EngineerLocation: Banglaore/HyderabadEmployment Type: Full-timeIndustry: Semiconductors / VLSI / ASIC DesignJob Summary:We are looking for a skilled and motivated STA Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting...
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STA & Synthesis Engineer
1 week ago
bangalore district, India ACL Digital Full timeLooking for STA & Synthesis Engineer. Exp.-3.5+yrs. Job Location- Bangalore. Notice Period- Prefer Immediate joiner or less notice period. Netlist and constraint sign in checks and validation. Responsible to complete synthesis till final-opt with DFT insertion Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power...
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Senior/Lead STA engineer
1 week ago
bangalore district, India ACL Digital Full timeWe’re Hiring: STA Engineer | 5–15 Years Experience | Bangalore Company: ACL Digital Company Location: Bangalore Experience: 5 to 15 Years Job Type: Full-Time ACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced SoC designs. If you’re an STA expert who thrives in fast-paced,...
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STA Engineer
6 days ago
Bangalore Division, India ACL Digital Full timeJob Title: STA Engineer Location: Banglaore/Hyderabad Employment Type: Full-time Industry: Semiconductors / VLSI / ASIC Design Job Summary: We are looking for a skilled and motivated STA Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting...
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STA Engineers
2 weeks ago
bangalore, India LeadSoc Technologies Pvt Ltd Full timeStatic Timing Analysis (STA) Engineer Job Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and...
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Static Timing Analysis
1 week ago
bangalore district, India LeadSoc Technologies Pvt Ltd Full timeStatic Timing Analysis (STA) Engineer Job Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and...
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Senior STA Architect
1 week ago
bangalore district, India Eximietas Design Full timeHello All, Eximietas Design Hiring STA Engineers/Leads Experience: 8+ Years. Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA. Anyone with a Valid H1B or Already in US. Job Description: Experience in Static Timing Analysis (STA) for ASIC designs. Experience in developing timing constraints. Experience in timing closure and...
