STA Engineers
2 weeks ago
Static Timing Analysis (STA) Engineer Job Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and physical design teams to achieve the target operating frequency and performance metrics. Key Responsibilities Timing Sign-off and Analysis Timing Closure Ownership: Drive all aspects of timing closure from pre-layout to post-layout for blocks, sub-systems, and/or the full chip. Constraint Management: Develop, validate, and maintain Synopsys Design Constraints (SDC) and timing constraints for all functional and test modes (e.g., Scan, MBIST). MMMC Analysis: Perform comprehensive timing analysis across multiple operating corners (Process, Voltage, Temperature - PVT) and various modes (Multi-Mode Multi-Corner). Critical Path Identification: Analyze timing reports to identify and debug critical paths and resolve all Setup and Hold violations. Signal Integrity (SI) & Noise: Incorporate advanced timing effects such as on-chip variation (OCV), signal integrity (crosstalk), and voltage drop (IR-drop aware STA) into the sign-off process. Methodology and Flow Develop, maintain, and enhance STA flows and methodologies to improve efficiency, robustness, and reduce analysis runtime. Automate repetitive tasks and report generation using scripting languages. Generate final timing reports and sign-off collateral for tape-out. Education Bachelor's or Master's degree in Electrical Engineering (EE), Electronics Engineering, VLSI, or a related field. Technical Skills & Experience Experience: 3+ years of experience in STA. EDA Tools: Expert proficiency with industry-standard Electronic Design Automation (EDA) tools from vendors like Synopsys (e.g., Fusion Compiler, ICC2, Primetime), Cadence (e.g., Innovus), or Mentor Graphics. Soft Skills Excellent analytical, debugging, and problem-solving skills. Strong verbal and written communication skills. Ability to work effectively in a team environment and collaborate across different engineering disciplines. Experience Level :- 3yrs to 15yrs Notice Period :- Immediate to 60 Days Work Location :- Bangalore Mode of Work :- WFO Employment Type :- Permanent
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STA CAD Engineer
5 hours ago
bangalore district, India ACL Digital Full timeGreetings from ACL Digital We are looking for STA CAD Engineers. Experience Level:4+ years of STA CAD Job Description: STA CAD Engineer Location: Hyderabad and Bangalore Job Description: Bachelor's degree in Electrical or Computer Engineering and 4+ years STA (Timing, Constrains)/CAD experience or Master's degree and 2+ years' experience • Excellent...
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STA Engineer
7 hours ago
bangalore, India Mirafra Technologies Full timeSTA Engineer | Noida, Bangalore (3-10 Yrs) & PTPX Engineer (10 Years) | BangaloreWe are looking for skilled STA / PTPX Engineers with strong experience in timing sign-off and power analysis. Key Skills:• STA sign-off, MCMM timing closure• PrimeTime / PrimeTime-SI / PrimeTime-PX• PTPX power analysis (dynamic & static)• Timing constraints, ECOs,...
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STA Engineer
7 days ago
bangalore, India Mirafra Technologies Full timeSTA Engineer | Noida, Bangalore (3-10 Yrs) & PTPX Engineer (10 Years) | BangaloreWe are looking for skilled STA / PTPX Engineers with strong experience in timing sign-off and power analysis. Key Skills:• STA sign-off, MCMM timing closure• PrimeTime / PrimeTime-SI / PrimeTime-PX• PTPX power analysis (dynamic & static)• Timing constraints, ECOs,...
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STA Engineer
7 days ago
bangalore, India Mirafra Technologies Full timeSTA Engineer | Noida, Bangalore (3-10 Yrs) & PTPX Engineer (10 Years) | Bangalore We are looking for skilled STA / PTPX Engineers with strong experience in timing sign-off and power analysis.🛠️ Key Skills: • STA sign-off, MCMM timing closure • PrimeTime / PrimeTime-SI / PrimeTime-PX • PTPX power analysis (dynamic & static) • Timing constraints,...
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STA Engineer
7 days ago
Bangalore, India Mirafra Technologies Full timeSTA Engineer | Noida, Bangalore (3-10 Yrs) & PTPX Engineer (10 Years) | Bangalore We are looking for skilled STA / PTPX Engineers with strong experience in timing sign-off and power analysis. 🛠️ Key Skills: • STA sign-off, MCMM timing closure • PrimeTime / PrimeTime-SI / PrimeTime-PX • PTPX power analysis (dynamic & static) • Timing constraints,...
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STA Engineer
6 days ago
Bangalore, India Mirafra Technologies Full timeSTA Engineer | Noida, Bangalore (3-10 Yrs) & PTPX Engineer (10 Years) | Bangalore We are looking for skilled STA / PTPX Engineers with strong experience in timing sign-off and power analysis.
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STA & Synthesis Engineer
2 weeks ago
bangalore district, India ACL Digital Full timeLooking for STA & Synthesis Engineer. Exp.-3.5+yrs. Job Location- Bangalore. Notice Period- Prefer Immediate joiner or less notice period. Netlist and constraint sign in checks and validation. Responsible to complete synthesis till final-opt with DFT insertion Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power...
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STA Engineer
7 days ago
Bangalore Urban, India Mirafra Technologies Full timeSTA Engineer | Noida, Bangalore (3-10 Yrs) & PTPX Engineer (10 Years) | Bangalore We are looking for skilled STA / PTPX Engineers with strong experience in timing sign-off and power analysis.🛠️ Key Skills: • STA sign-off, MCMM timing closure • PrimeTime / PrimeTime-SI / PrimeTime-PX • PTPX power analysis (dynamic & static) • Timing constraints,...
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STA Engineer
7 days ago
Bangalore Urban, India Mirafra Technologies Full timeSTA Engineer | Noida, Bangalore (3-10 Yrs) & PTPX Engineer (10 Years) | Bangalore We are looking for skilled STA / PTPX Engineers with strong experience in timing sign-off and power analysis.
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STA Engineer
6 days ago
Bangalore, India ACL Digital Full timeRole: STA Engineer Experience: 3+ Years Location: Bangalore (Onsite) Notice Period: Immediate to 30 Days / Serving Notice Key Responsibilities: Perform Static Timing Analysis (STA) at block and full-chip levels across multiple design stages (synthesis, P&R, sign-off). Develop, validate, and maintain timing constraints (SDC files) for complex SoC and IP-level...
