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vellore, India beBeeVerification Full time

Job Description:The Senior Design Verification Lead is responsible for leading SoC design verification efforts for complex projects, ensuring the successful execution of verification plans, including test plans, testbenches, and coverage analysis for both high-speed and low-speed peripherals (e.g., I2C, SPI, UART, GPIO, QSPI) as well as high-speed protocols (e.g., PCIe, Ethernet, CXL, MIPI, DDR, HBM).Key Responsibilities:Develop comprehensive verification strategies, collaborating closely with cross-functional teams, including architects, designers, and pre/post-silicon verification teams, to ensure alignment and seamless integration of verification efforts.Analyze and implement System Verilog assertions and functional coverage to ensure thorough verification of design functionality, providing mentorship and technical guidance to junior verification engineers.Manage a dynamic team of verification engineers, fostering a collaborative and innovative work environment, upholding quality standards and implementing best test practices.Work with verification tools from Synopsys and Cadence, integrating third-party VIPs to enhance verification coverage.Requirements:Proven experience in leading SoC design verification effortsExpertise in System Verilog assertions and functional coverageStrong leadership and collaboration skillsAbility to manage multiple projects simultaneouslyBenefits:Opportunity to work on complex and challenging projectsCollaborative and dynamic work environmentProfessional growth and development opportunitiesCompetitive salary and benefits package

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