Design Verification Engineer

4 days ago

bangalore, India Client of connectpro Full time

- 9+ years of experience in Functional Verification of processors or ASICs.
- 3+ years of experience in the following areas
- Computer architecture knowledge.
- Multi-processor Cache Coherency Transport Network on Chip Memory Hierarchy verification.
- AXI,AHB,ACE,ACE-lite/CHI/On Chip System Fabric interface verification or any other Processor/SoC coherency transport interconnect fabric verification.
- Knowledge of performance parameters of On Chip Coherency Transport Network designs and ways to stress verify them
- Minimum one full life cycle leadership experience of a processor/SoC verification flow with focus on Coherency Transport Interconnect and/or Network on Chip Verification
- Good object-oriented programming skills in C++/SystermVerilog, scripting languages like Python/Perl.
- Verification knowledge in Clock domain crossing and reset domain crossing
- Knowledge of functional verification methodology like UVM/OVM
- Knowledge of HDLs (VHDL/Verilog)
- Developed test plans and test strategies for IP/unit/block level verification of Coherency Transport Interconnects
- Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow
- Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails
- Experience in driving verification coverage closure including performance testing, stress testing and ability to identify corner case scenarios.

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