High-Speed Analog Circuit Designer

2 weeks ago

palakkad, India beBeeAnalogEngineer Full time

About the CompanyWe are seeking a Senior Analog Layout Engineer to work on high-speed analog chip development in advanced TSMC 5nm technology. The candidate will operate as an individual contributor, responsible for delivering complex high-speed analog and mixed-signal layout blocks with minimal supervision.Job Description – Senior Analog Layout Engineer (8 to 17 Years Experience)Position: Senior Analog Layout / IP Delivery EngineerExperience Required: 8+ YearsLocation: RemoteRole OverviewWe are looking for a highly experienced Senior Analog Layout Engineer with strong expertise in chip-level handling of high-speed analog IPs, deep understanding of ICC2-based top-level integration, and the ability to independently run block-level simulations.The candidate must have very strong IP verification knowledge and experience coordinating with foundry teams for signoff, tape-out, and model-related interactions. This role requires full ownership of IP development, verification, integration, and delivery.Key ResponsibilitiesHandle chip-level planning and integration of high-speed analog IPsPerform complete analog layout design including floorplanning, routing, matching, shielding, EM/IR checks, and parasitic optimizationRun post-layout simulations (extracted netlist, corners, Monte Carlo) and ensure correlation with schematicStrong understanding of ICC2 flows for complete SoC/top-level integrationLead IP verification, including DRC, LVS, ERC, ANT, PEX, and reliability checksDrive complete IP signoff ownership, ensuring zero violations at final GDS deliveryWork closely with foundry teams for:· PDK clarifications· LVS/DRC rule updates· Model issues and PEX rule discussions· Tape-out requirements and signoff guidelines· Coordinate with PD, DV, circuit design, and packaging teams for smooth IP-level delivery· Prepare and deliver IP documentation, abstracts, verification reports, and GDSRequired Skills and Qualifications8+ years of solid experience in Analog/Mixed-Signal LayoutDeep expertise in high-speed IPs (SERDES, PLL, ADC/DAC, Tx/Rx, clocking blocks)Strong understanding of chip-level integration, hierarchy, and physical interfacesHands-on experience with ICC2 and top-level integration flowsAbility to run simulations for the blocks being designed (post-layout, extracted)Very detailed understanding of:o IP-level verificationo DRC/LVS/ERCo PEX/RC extractiono Signoff decks & reliability checksBenefitsThis role offers excellent opportunities for professional growth and career advancement in the field of analog IC design. If you have a passion for designing high-speed analog circuits and working collaboratively with a team of experts, we encourage you to apply.OthersMandatory experience in TSMC 5NM. Excellent command of Cadence Virtuoso, PVS, Calibre, and extraction tools.

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