Full Chip Physical Design Lead

Job OpportunityWe are seeking a seasoned expert to lead full-chip static timing analysis (STA) efforts. The ideal candidate will have strong expertise in constraint management, cross-functional collaboration, and driving timing closure activities for complex system-on-chip (SoC) designs.Key ResponsibilitiesDevelop and implement effective constraints at the...

Job Overview:We are seeking a seasoned Physical Design Engineer to lead the development of innovative designs at the 10nm/7nm/5nm or lower nodes.This role requires expertise in solving complex design problems to achieve desired performance, area, and power targets.Key Responsibilities Include:Developing cutting-edge placement, CTS, and routing methodologies...

🚀 Eximietas is Hiring – Senior Physical Design Architects. Experience: 15+ Years📍Locations:Bengaluru, IndiaVisakhapatnam, IndiaSan Jose (Bay Area), USAAustin, USAEligibility (US Roles): Valid H1B or candidates already in the U.S.Qualifications:Bachelor’s or Master’s degree in Electronics, Electrical, Telecom, or VLSI EngineeringMinimum 15+ years...

At the forefront of semiconductor innovation, we seek an accomplished Full Chip STA Strategist to drive cutting-edge timing closure solutions for complex SoCs.This pivotal role necessitates a seasoned professional with profound expertise in full-chip timing, constraint management, and collaborative engineering practices.Ambitious Responsibilities:Lead static...

Job Title:Senior RTL Design EngineerJob Description:As a senior-level designer, you will lead the development of complex System-on-Chip (SoC) designs. This role requires expertise in logic design, register-transfer level (RTL) coding, and Verilog/System-Verilog. Additionally, knowledge of multi-clock designs, asynchronous interfaces, and ASIC development...

eInfochips (An Arrow Company) Hiring Physical Design EngineerExperience - 4+ YearsLocation- NoidaJob description is as below:* Block level Physical Design Implementation from RTL to GDSII or Netlist to GDSII,* Block level Physical Signoff,* Block level Timing Signoff and ECO generation.* Block level Power signoff.* Good skill on Automation...

Job Overview:The selected candidate will be responsible for leading a team of engineers in the implementation of physical design and signoff processes.Key Responsibilities:Implement block-level physical design from RTL to GDSII or netlist to GDSIILead a team of 4-6 engineers in achieving project goalsCollaborate with clients as a single point of contact for...

Senior Analog Layout Engineer (8–17 Years Experience)Job Type: Full-TimeWe are seeking a highly experienced Senior Analog Layout / IP Delivery Specialist with strong expertise in designing and integrating high-speed analog IPs at the chip level.This role requires deep knowledge of ICC2-based top-level integration, extensive IP verification experience, and...

Drive timing closure activities for complex SoCs and provide technical guidance to junior engineers.Handle functional and test constraints at block and top levelPerform static timing analysis (STA) for block-level and full-chip sign-offOwn ECO generation at the top level and coordinate with block owners for timing/functional ECO implementationWork closely...

Senior Verification Engineer for System-on-Chip (SoC) DesignsThis role offers a unique opportunity to lead the development of cutting-edge SoC designs, working closely with cross-functional teams to drive product validation and customer engagement.The team utilizes processes from semiconductor and hardware systems design to reduce bugs, improve efficiency,...