Digital Fault Tolerant Engineer

5 days ago

Kolhapur, India beBeeDigitalFaultTolerance Full time

Lead Digital Fault Tolerant EngineerWe are seeking an experienced Digital Fault Tolerant engineer to join our team.The ideal candidate will have a deep understanding of digital fault tolerant techniques and methodologies, including scan insertion, compression, ATPG, MBIST, and boundary scan. They will be responsible for developing and implementing DFT strategies and architectures for complex ASIC/SoC designs, as well as mentoring junior engineers and collaborating with cross-functional teams.Key Responsibilities:DFT Strategy and Architecture: Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.Scan Insertion and Compression: Lead implementation and verification of scan insertion and compression (e.g., EDT) features.ATPG Pattern Generation: Generate and implement ATPG patterns for fault grading.MBIST and Logic BIST: Manage the insertion and validation of MBIST and logic BIST features.Boundary Scan: Implement and verify boundary scan (IEEE 1149.1/1149.6) and IJTAG (1687).DFT Flow Management: Own end-to-end DFT flow — from RTL to gate-level netlist and silicon bring-up.Cross-Functional Collaboration: Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.Pattern Generation and Debug: Perform pattern generation, fault simulation, and debug test coverage gaps.DFT Signoff and Timing Closure: Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.Silicon Bring-Up and Yield Optimization: Support silicon bring-up, test vector validation on ATE, and yield optimization.Mentorship and Training: Mentor and guide junior DFT engineers; conduct design reviews and training sessions.DFT Automation: Develop and maintain DFT automation scripts and infrastructure.Required Skills and Qualifications:Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design.7+ years of experience in DFT for complex ASIC or SoC designs.Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.Familiarity with DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX, Siemens EDA: Tessent ScanPro, MBIST, IJTAG, Cadence/others: Modus, Encounter Test.Strong knowledge of RTL design, STA, and synthesis flows.Proficient in scripting languages (Python, Perl, Tcl) for flow automation.Deep understanding of silicon test challenges and test coverage improvement.Strong leadership, team collaboration, and communication skills.Preferred Qualifications:Experience with hierarchical DFT and low-power DFT methodologies (UPF).Exposure to post-silicon validation and failure analysis.Familiarity with safety-critical designs (ISO 26262) and functional safety.Experience working in advanced nodes (e.g., 7nm, 5nm, FinFET).Why Join Us?Work on high-performance, next-gen SoCs and ASICs.Collaborate with top-tier engineers and global semiconductor leaders.Competitive salary, leadership exposure, and fast-track growth opportunities.

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