High-Speed Analog Layout Expert

2 weeks ago

meerut, India beBeeEngineer Full time

About this positionWe are seeking an experienced Senior Analog Layout Engineer to work on high-speed analog chip development in advanced technology.The ideal candidate will have deep technical expertise in chip-level integration, bump planning, and ESD implementation, along with a good understanding of circuit simulation concepts.This role requires close collaboration with SoC, Circuit, and Digital teams to ensure robust layout quality and performance.Key responsibilities include handling chip-level planning and integration of high-speed analog IPs, performing complete analog layout design including floorplanning, routing, matching, shielding, EM/IR checks, and parasitic optimization.The selected candidate must have very strong IP verification knowledge and experience coordinating with foundry teams for signoff, tape-out, and model-related interactions.This role requires full ownership of IP development, verification, integration, and delivery.Key Responsibilities:Handle chip-level planning and integration of high-speed analog IPs.Perform complete analog layout design including floorplanning, routing, matching, shielding, EM/IR checks, and parasitic optimization.Run post-layout simulations (extracted netlist, corners, Monte Carlo) and ensure correlation with schematic.Strong understanding of ICC2 flows for complete SoC/top-level integration.Lead IP verification, including DRC, LVS, ERC, ANT, PEX, and reliability checks.Drive complete IP signoff ownership, ensuring zero violations at final GDS delivery.Work closely with foundry teams for PDK clarifications, LVS/DRC rule updates, model issues, and PEX rule discussions.Cordinate with PD, DV, circuit design, and packaging teams for smooth IP-level delivery.Prepare and deliver IP documentation, abstracts, verification reports, and GDS.Required Skills and Qualifications:8+ years of solid experience in Analog/Mixed-Signal Layout.Deep expertise in high-speed IPs (SERDES, PLL, ADC/DAC, Tx/Rx, clocking blocks).Strong understanding of chip-level integration, hierarchy, and physical interfaces.Hands-on experience with ICC2 and top-level integration flows.Ability to run simulations for the blocks being designed (post-layout, extracted).Very detailed understanding of IP-level verification, DRC/LVS/ERC, PEX/RC extraction, signoff decks & reliability checks.Proven experience interacting with foundry teams for rule clarifications and IP/tape-out signoff.Excellent command of Cadence Virtuoso, PVS, Calibre, and extraction tools.Benefits:Experience with advanced nodes (5nm).Exposure to SERDES / PCIe / MIPI / USB high-speed IPs.Experience working with global customers.Travel: Willing to travel to the U.S. for project release (as required)Equal Opportunity Statement: We are committed to diversity and inclusivity.

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