Digital Logic Architect

Job DescriptionOur organization is seeking a highly skilled RTL Design Engineer with expertise in Verilog/RTL design for IP or SoC. This role involves leading the development of complex digital logic designs, collaborating with cross-functional teams, and ensuring timely delivery of high-quality results.Key Responsibilities:Design and develop RTL code for IP blocks and SoCs using industry-standard tools like Synopsys/Cadence/Mentor.Collaborate with design teams to identify areas for improvement and implement changes to enhance overall system performance.Develop and maintain thorough knowledge of digital logic design concepts, including but not limited to, HDL languages (Verilog/VHDL), clock domain crossing, and power management.Requirements:Minimum 7 years of experience in RTL design with at least one large IP block under their belt.Strong command over digital logic design concepts, including HDL languages, clock domain crossing, and power management.Expertise in simulation tools (Synopsys/Cadence/Mentor) and debugging skills.Desirable experience in Perl/TCL scripting and automation knowledge, as well as RTL logic synthesis, sdc, and constraint writing.Understanding of basic soc architecture std-cells, IO blocks, etc.What We Offer:Our organization is committed to providing a challenging and rewarding work environment that fosters growth and development. If you are a motivated and experienced professional looking for a new challenge, we encourage you to apply for this exciting opportunity.