Sr Engineering Manager: Silicon Validation: Analog/ PMIC: Bench Validation

6 days ago

bangalore, India Cyient Full time

Hi Arun


As per our discussion, We, Cyient is hiring for one of the Senior Leadership position: Sr Engineering Manager: Silicon Validation: Analog/ PMIC: Bench Validation & Characterization (Offshore-Onshore Model based Global Product Solution) Position.


Base Location: Bangalore

Experience Range: 18-30 Years


Job Description:


  • As a Sr Engineering Manager, we are looking for specialized resource in Advanced Analog Validation, Applicant must have strong experience in Project Planning and Execution from Scratch with Customer Interface Experience.
  • Will Lead Bench Characterization for Analog IPs in SoC
  • Will Lead the new team to successful and timely completion of bench characterization of analog IPs such as ADC, DAC, LDO, Thermal Sensor, CMPSS, Bandgap, Oscillator
  • Will be involved in Improving test flows, automations, test board, instrument usage optimization, team knowledge to achieve robust, efficient and optimal test setups
  • Will be involved in Planning for fastest Si-to-RTM cycle in next SoC
  • Must have worked on pre-Si SoC level validation of digital interfaces for analog IPs: ADC, DAC, CMPSS, TSENSE
  • Must have understanding of end-equipment and use-case of Resolver IP, working on demo setup for the same
  • Will be responsible for characterization of PLL, Thermal Sensor, OTP, GPIO, MTBF, PMB, RO, Oscillator, Filter, BBGEN
  • Must have understanding of VIL/VIH, VOL/VOH, Rise-time, Fall-time, Propagation-Delay, Jitter, Phase Noise, PSRR, Lock-Time etc.
  • Should have created automations using LabVIEW, VB, Python
  • Must have knowledge of block level design of analog IPs o Created first time setup for PLL, TSense, BBGEN, OTP
  • Must have trained new employees


Best Regards

Rajani Kant Sharma

Sr Recruiter: Global Lateral Hiring: Semicon Vertical

Cyient

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