Advanced Semiconductor Timing Analysis Specialist
3 days ago
Job DescriptionAs a seasoned expert in full-chip static timing analysis (STA), you will be responsible for leading complex timing closure activities for sophisticated system-on-chips (SoCs). Your technical prowess in constraint management and cross-functional collaboration will drive the success of our cutting-edge semiconductor development projects.Key responsibilities include:Handling functional and test constraints at block and top levels to ensure seamless integrationPerforming static timing analysis (STA) for block-level and full-chip sign-off, guaranteeing timely delivery and high-quality resultsOverseeing ECO generation at the top level and coordinating with block owners for timely implementation of timing/functional changesCollaborating closely with synthesis teams for block-level and top-level synthesis to optimize performance and power consumptionDriving automation initiatives using Perl, Tcl, Awk, or Python to streamline processes and enhance productivityMentoring and guiding junior engineers on technical aspects, fostering a culture of knowledge sharing and growthRequired Skills and Qualifications8+ years of hands-on experience in full-chip STA, with a proven track record of delivering high-quality resultsExpertise in constraint handling, STA sign-off, and ECO flow, with a strong understanding of related technologies and toolsStrong scripting and automation skills, with experience in using languages like Perl, Tcl, Awk, or PythonExcellent communication and collaboration abilities, with a focus on building effective relationships with cross-functional teamsThis is an exceptional opportunity for a motivated and experienced professional to take their career to the next level. If you are passionate about driving innovation and excellence in the field of semiconductor development, we encourage you to apply.
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thane, India beBeeTiming Full timeJob SummaryThis role involves leading complex challenges in semiconductor development. As a senior STA expert, you will handle functional and test constraints at block and top levels.The ideal candidate will have experience with static timing analysis (STA) for sign-off and ECO flow implementation.Lead the generation of ECOs at the top level and coordinate...
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