Verification Engineer
2 months ago
Staff Engineer, SoC Verification.
Job Description and Requirements
The role is for SoC Verification in the System Solutions Group (SSG). The role primarily requires development and implementation of System Design Solutions using Synopsys EDA tools and IP to solve customer problems as part of a service project team.
The Systems Solutions Group (SSG) delivers tool, methodology, architecture, design creation, design verification and physical implementation expertise to enable leading edge customers to complete their most challenging SoC design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies. Our customers develop SOCs for high-performance computing, automotive, aerospace & defense, and more.
Responsibilities
Understand the design specification, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.
Responsible to implement and analyze system Verilog assertion and coverage (code, toggle, functional).
Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue.
Work as a lead, mentor young engineers and help them in debugging complex problems.
Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks.
Adhere to quality standards and good test and verification practices.
Ramp-up on new Verification tools and methodologies using Synopsys Products to enable customers.
Develop innovative solutions to problems with little guidance and implements them independently.
Set task-level goals and consistently meets schedules.
Work with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tool and IP solutions.
Required
B.E/B. Tech/M.E/M. Tech in electronics with 5-8 years of experience in verification domain.
Prior work experience on IP level or Soc level(Preferred) verification is must.
Good understanding of processor based Soc level verification which includes native ,Verilog ,system Verilog and UVM mix environment is desirable.
Hand on experience with verification tools such as VCS, waveform analyzer and third party VIP integration (such as Synopsys VIPs) is must.
Hands on experience in UVM. C/C++ ,System Verilog verification language.
Good understanding of AXI-AMBA protocol variants is a desirable.
Can work with scripting language (shell, Makefile, Perl )
Strong understanding of design concepts and ASIC flow.
Good problem solving , analytical and debugging skill is must.
Prior work on ARM core verification is desirable.
Prior work on USB, PCIe, MIPI Protocols is desirable.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
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