Lead Design Verification Engineer

2 months ago

bangalore, India Mulya Technologies Full time

Lead Design Verification Engineer

Location : Bangalore

Ventana Micro Systems is at the forefront of the two hottest trends that are revolutionizing the semiconductor industry: RISC-V and Chiplet Architecture. Check out our CEO talking with global tech analyst Patrick Moorhead about how Ventana combines the extensibility of RISC-V with chiplet technology to create customer-driven innovation for best-in-class solutions for the data center.

Ventana is well-funded and backed by some of the largest strategic investors in the industry with the goal of building best-in-class CPU cores for cloud, enterprise, 5G, and Edge computing. We invite you to join the revolution and contribute to one of the Hottest Semiconductor startups in the industry.

Lead Design Verification Engineer:

We are seeking an experienced verification engineer to lead verification efforts of complex IP subsystems based on the open-source RISC-V architecture. The right candidate will have deep technical expertise combined with exceptional leadership skills.

Responsibilities:

  • Lead end-to-end verification of complex IP subsystems partnering with architecture and design teams
  • Develop verification infrastructure components including test-benches, scoreboards, and stimulus generators
  • Develop and execute comprehensive verification plans for units and features
  • Implement functional coverage models
  • Debug designs in simulation, prototyping platforms, and silicon
  • Continuously drive methodology improvements to improve efficiency
  • Mentor junior engineers to build a high performing team

Minimum Qualifications:

  • Bachelors or Masters degree in electrical, computer engineering or related field
  • BS+8 years or MS+6 years of industry experience successfully delivering complex IP subsystems

Skills & Qualifications Required:

  • SystemVerilog verification development experience
  • Testbench construction using UVM or analogous methodologies
  • Scoreboards and stimulus generators for complex units
  • Strong background in industry standards and protocols such as PCIe, Ethernet, CXL, AMBA AXI etc.,
  • Unit or feature ownership throughout the project lifecycle
  • Demonstrated team leadership experience with outstanding communication skills
  • Highly motivated self-starter with strong execution mindset and collaborative approach
  • Post-silicon debug experience strongly preferred


Contact:

Uday

Mulya Technologies

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