Full Chip STA Lead Position

3 days ago


erode, India beBeeTimingEngineer Full time

Senior Timing EngineerWe are seeking a seasoned Senior Timing Engineer to lead full-chip timing analysis and constraint management initiatives.Manage functional and test constraints at the block and top levelsPerform static timing analysis (STA) for blocks and the full chip, ensuring sign-off qualityOwn ECO generation at the top level and coordinate with block owners for timing/functional implementationCollaborate closely with synthesis teams for block-level and top-level synthesisDrive automation initiatives using scripting languages like Perl, Tcl, Awk, or PythonMentor junior engineers on technical aspects of STA and constraint managementRequirements:8+ years of hands-on experience in full-chip STA, preferably with expertise in constraint handling and ECO flowsProven skills in scripting and automationExcellent communication and collaboration abilities



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