ASIC RTL Engineer

Opportunity With Tessolve Semiconductor- Bangalore Hi All, we are hiring RTL design engineer and design verification engineer for Bangalore location. Exp: 5+ yr exp Skills: RTL ASIC, CDC, Lint, Synthesis, Spyglass We are hiring for RTL ASIC engineer 7f work experience in ASIC/IP Design. Experience in Logic design / RTL design Experience is IP design...

Key skills with hand on: ASIC,RTL Design, VLSI-SOC ,AMBA, Lint, CDC, Synopsys LintCDC/VerdiXcellium/Synopsys DC. Experience: 5 - 25 years Work Location: Trivandrum, Bangalore, Hyderabad, Chennai, Pune Education: Engineering (excluding Mechanical/Civil) Detailed JD: IP RTL design targeted for SOC, Static checks, some basic protocols Expertise in SoC...

RTL Design: Design and implement RTL code for ASICs in Verilog or SystemVerilog. Create high-quality, reusable, and maintainable RTL code for complex digital systems. Architecture Design: Work closely with architects to understand the high-level design specifications and translate them into efficient RTL code. Participate in defining micro-architecture for...

Senior ASIC/So C RTL Engineer/Lead (IP RTL design targeted for SOC, Static checks, some basic protocols) Exp - 4 - 20 Location : Bengaluru, Hyderabad, Pune, Noida, Kochi Expertise in So C subsystem/IP design Expertise in IP design, Subsystem/Cluster and So C level integration using Verilog/System Verilog In depth knowledge on RTL quality checks (Lint,...

Key skills with hand on: ASIC, RTL Design, VLSI-SOC , AMBA, Lint, CDC, Synopsys Lint CDC/Verdi Xcellium/Synopsys DC. Experience: 5 - 25 years Work Location: Trivandrum, Bangalore, Hyderabad, Chennai, Pune Education: Engineering (excluding Mechanical/Civil) Detailed JD: IP RTL design targeted for SOC, Static checks, some basic protocols Expertise in...

Opportunity With Tessolve Semiconductor- Bangalore Hi All, we are hiring RTL design engineer and design verification engineer for Bangalore location. Exp: 5+ yr exp Skills: RTL ASIC, CDC, Lint, Synthesis, Spyglass We are hiring for RTL ASIC engineer 7f work experience in ASIC/IP Design. Experience in Logic design / RTL design Experience is IP design...

ASIC Design Engineer We are seeking a skilled ASIC Design Engineer with a solid background in digital design , RTL coding , and ASIC development . The ideal candidate will have extensive experience in designing, developing, and optimizing high-performance ASICs, with a strong focus on SystemVerilog or VHDL . This role will involve taking...

Hi All, Eximietas: Eximietas Design is a leading technology consulting and solutions development firm specializing in the VLSI, Cloud Computing, Cyber Security, and AI/ML domains. We are Hiring: Senior ASIC SOC RTL Design Leads Location: Visakhapatnam or Bangalore Experience: 10+ Years. ❖ Minimum Qualifications: Bachelor's degree in Computer Science,...

Senior ASIC/SoC RTL Engineer/Lead (IP RTL design targeted for SOC, Static checks, some basic protocols) Exp - 4 - 20 Location :Bengaluru, Hyderabad, Pune, Noida, Kochi Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog In depth knowledge on RTL quality checks...

Senior ASIC/SoC RTL Engineer/Lead (IP RTL design targeted for SOC, Static checks, some basic protocols) Exp - 4 - 20 Location :Bengaluru, Hyderabad, Pune, Noida, Kochi Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog In depth knowledge on RTL quality checks...