Ciliconchip Chief Technology Officer

Role: Chief Technology OfficerExperience: 20+ YearsLocation: BangaloreRole Overview:The Chief Technology Officer (CTO) will define and lead the company’s technology vision,architecture, and innovation roadmap in Mixed-Signal Analog IP development, with focusareas spanning power management, UCIe interfaces, memory, and sensor technologies.This leadership role will drive R&D excellence, IP innovation, and engineering capability acrossglobal design teams.Key Responsibilities:1. Technology Strategy & Vision● Define and own the company’s Mixed-Signal Analog IP technology roadmap, aligningit with business strategy and market direction.● Identify emerging analog and mixed-signal trends (UCIe, chiplet integration,low-power and high-speed analog architectures) that can create competitivedifferentiation.● Establish and nurture strategic partnerships with foundries, EDA vendors, universities,and ecosystem players to strengthen IP innovation.● Guide R&D in advanced design methodologies, reusable IP frameworks, andnext-generation process readiness.2. Engineering Leadership● Oversee all engineering functions — Analog/Mixed-Signal Design, CircuitVerification, Layout, Validation, and Integration.● Set technical standards, design quality metrics, and best practices across all IPdevelopment programs.● Ensure predictable execution and delivery of high-performance, low-powerMixed-Signal IPs.● Drive PPA (Power, Performance, Area) optimization, design reusability, andautomation in design and verification flows.3. IP Development & Productization● Drive first-silicon success and productization of advanced Mixed-Signal IPs acrosspower, UCIe, memory, and sensor domains.● Architect reusable IP cores, subsystems, and platforms to accelerate future productand customer integration cycles.● Oversee technology evaluation for EDA tools, analog/mixed-signal design kits (PDKs),libraries, and process migrations.● Review IP specifications to ensure feasibility, scalability, manufacturability, andcompliance with integration standards.4. Innovation & R&D● Lead advanced R&D initiatives in emerging domains such as low-power architectures,high-speed interfaces, and AI-assisted design automation.● Sponsor internal innovation programs and IP filings, fostering a culture of technicalexcellence and experimentation.● Drive internal architecture forums, design councils, and cross-functional technicalreviews to accelerate learning and innovation.5. Talent Development & Organization Building● Mentor and develop senior technical leaders including Directors, Fellows, andPrincipal Engineers across analog, mixed-signal, and IP disciplines.● Foster a high-performance, innovation-driven culture emphasizing accountability andtechnical depth.● Partner with HR to define technical career ladders, learning frameworks, anduniversity collaboration programs to build a sustainable talent pipeline.6. Customer & Ecosystem Engagement● Serve as the company’s technical ambassador with customers, partners, and industryforums.● Translate customer requirements into scalable, IP-level technical solutions androadmaps.● Engage in strategic business reviews, co-development initiatives, and customerengagements to ensure alignment with market needs.● Represent the company at industry conferences and technology consortia,showcasing IP leadership and innovation.7. Governance & Risk Management● Ensure IP protection, design security, and compliance across all programs.● Define and enforce technical governance frameworks, including design reviews andquality audits.● Mitigate risks through robust validation, simulation coverage, and silicon correlationstrategies.Qualifications:Minimum Requirements● B.E./B.Tech/M.Tech/Ph.D. in Electrical, Electronics, or MicroelectronicsEngineering.● 20+ years of experience in Analog/Mixed-Signal IP design and development, with atleast 10 years in senior leadership roles.● Proven track record of leading large, multi-disciplinary engineering teams acrossglobal sites.● Deep hands-on expertise in power management circuits, high-speed interfaces(UCIe), memory IPs, and sensor integration.● Strong understanding of EDA tool chains, design flows, process technologies, andsilicon manufacturing.● Demonstrated success in building world-class engineering teams and delivering IPinnovation at scale.Please reach out to varun@ciliconchip.com