RTL FPGA Engineer with HAPS prototyping

3 days ago


bangalore, India Proxelera Full time

Job Description Role : RTL FPGA Engineer with HAPS prototyping experience Roles and Responsibilities : Experience: 5-10YrsWork location: Bangalore 5–10 years’ hands-on experience with Synopsys HAPS boards and ProtoCompiler/Identify Debug. Strong RTL design/verification skills in Verilog/SystemVerilog. Proven FPGA implementation expertise: synthesis, floorplanning, SDC constraints, and timing closure. Board-level bring-up/debug using JTAG, oscilloscopes, logic analyzers; solid clocks/resets/power understanding. Interface bring-up experience with PCIe, DDR, Ethernet, and common serial buses (UART/SPI/I2C). Scripting proficiency in TCL, Python, and Shell for flow automation. Excellent problem-solving, cross-functional communication, and documentation skills.



  • bangalore district, India Proxelera Full time

    Job Description Role : RTL FPGA Engineer with HAPS prototyping experience Roles and Responsibilities : Experience: 5-10Yrs Work location: Bangalore 5–10 years’ hands-on experience with Synopsys HAPS boards and ProtoCompiler/Identify Debug. Strong RTL design/verification skills in Verilog/SystemVerilog. Proven FPGA implementation expertise: synthesis,...


  • bangalore, India Proxelera Full time

    RTL FPGA Engineer with HAPS prototyping experience Experience: 5-10Yrs Work location: BangaloreRoles and Responsibilities: 5–10 years’ hands-on experience with Synopsys HAPS boards and ProtoCompiler/Identify Debug. Strong RTL design/verification skills in Verilog/SystemVerilog. Proven FPGA implementation expertise: synthesis, floorplanning, SDC...


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  • bangalore district, India Proxelera Full time

    RTL FPGA Engineer with HAPS prototyping experience Experience: 5-10Yrs Work location: Bangalore Roles and Responsibilities: 5–10 years’ hands-on experience with Synopsys HAPS boards and ProtoCompiler/Identify Debug. Strong RTL design/verification skills in Verilog/SystemVerilog. Proven FPGA implementation expertise: synthesis, floorplanning, SDC...

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