Synthesis Engineer
3 days ago
Job Description – Senior Synthesis Engineer (VLSI)Position OverviewWe are seeking a highly motivated and experienced Senior Synthesis Engineer with a strong background in VLSI design. The ideal candidate will have hands-on expertise in advanced technology nodes, physical synthesis, low-power methodologies, and cross-functional collaboration to meet aggressive PPA targets.Key ResponsibilitiesPerform RTL-to-Gate Synthesis and Physical Synthesis across multiple corners and modes (MCMM) using industry-standard tools such as Fusion Compiler or Genus.Drive timing closure, power optimization, and area reduction to achieve design PPA goals.Conduct Logic Equivalence Check (LEC) and low-power structural checks using tools like Conformal LEC or Formality, and debug issues to ensure clean signoff.Perform pre-STA timing analysis using PrimeTime or Tempus.Run and analyze low-power verification checks using Conformal Low Power (CLP) or VCLP.Verify constraints quality and completeness and ensure design compliance with spec.Work with UPF and low-power design concepts throughout the synthesis and signoff process.Support functional ECO flows and implement ECO changes with minimal impact on PPA.Collaborate with RTL, DFT, and Physical Design teams to debug issues and ensure smooth handoff.Provide input and debugging support for DFT insertion and basic DFT-related challenges.Develop and maintain automation using TCL/Perl/Shell scripting to enhance productivity and design quality.Required QualificationsBachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or a related field.Minimum 3+ years of experience in Synthesis and Physical Synthesis.Hands-on experience with advanced technology nodes (7nm, 5nm, or below).Strong understanding of low power design, UPF, and multi-mode/multi-corner analysis.Proven debugging, analytical, and problem-solving skills.Self-driven with strong initiative, ownership, and the ability to work in fast-paced environments.
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Synthesis Engineer
1 day ago
Bangalore, India LeadSoc Technologies Pvt Ltd Full timeJob Description – Senior Synthesis Engineer (VLSI) Position Overview We are seeking a highly motivated and experienced Senior Synthesis Engineer with a strong background in VLSI design. The ideal candidate will have hands-on expertise in advanced technology nodes, physical synthesis, low-power methodologies, and cross-functional collaboration to meet...
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Synthesis Engineer
3 days ago
bangalore, India LeadSoc Technologies Pvt Ltd Full timeJob Description – Senior Synthesis Engineer (VLSI)Position OverviewWe are seeking a highly motivated and experienced Senior Synthesis Engineer with a strong background in VLSI design. The ideal candidate will have hands-on expertise in advanced technology nodes, physical synthesis, low-power methodologies, and cross-functional collaboration to meet...
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Synthesis Engineer
1 day ago
Bangalore, India LeadSoc Technologies Pvt Ltd Full timeJob Description – Senior Synthesis Engineer (VLSI) Worked on 7nm/5nm/Future sub-micron Technologies. Hands on experience in Physical Synthesis with Multi corner & Multi-mode, Low Power, Performance and Area Goal using Fusion Compiler or Genus . Hands on experience in Logic equivalence check and low power check debugging and clean up using Conformal LEC or...
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Synthesis Engineer
5 days ago
Bangalore, India BITSILICA Full timeRequirement Details: Role: Synthesis Engineer Experience: 4+ years Location: Bangalore (Preferred) Skill Set: Hands-on experience in logic synthesis using Design Compiler Strong understanding of timing , low-power requirements , and constraints validation
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Synthesis Engineer
3 days ago
bangalore district, India LeadSoc Technologies Pvt Ltd Full timeJob Description – Senior Synthesis Engineer (VLSI) Position Overview We are seeking a highly motivated and experienced Senior Synthesis Engineer with a strong background in VLSI design. The ideal candidate will have hands-on expertise in advanced technology nodes, physical synthesis, low-power methodologies, and cross-functional collaboration to meet...
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Synthesis Engineer
3 days ago
bangalore, India BITSILICA Full timeRequirement Details:Role: Synthesis EngineerExperience: 4+ yearsLocation: Bangalore (Preferred)Skill Set:Hands-on experience in logic synthesis using Design CompilerStrong understanding of timing, low-power requirements, and constraints validation
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STA & Synthesis Engineer
5 days ago
Bangalore, India ACL Digital Full timeLooking for STA & Synthesis Engineer. Exp.-3.5+yrs. Job Location- Bangalore. Notice Period- Prefer Immediate joiner or less notice period. Netlist and constraint sign in checks and validation. Responsible to complete synthesis till final-opt with DFT insertion Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power...
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STA & Synthesis Engineer
3 weeks ago
Bangalore Division, India ACL Digital Full timeLooking for STA & Synthesis Engineer. Exp.-3.5+yrs. Job Location- Bangalore. Notice Period- Prefer Immediate joiner or less notice period. Netlist and constraint sign in checks and validation. Responsible to complete synthesis till final-opt with DFT insertion Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power...
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STA & Synthesis Engineer
3 days ago
bangalore district, India ACL Digital Full timeLooking for STA & Synthesis Engineer. Exp.-3.5+yrs. Job Location- Bangalore. Notice Period- Prefer Immediate joiner or less notice period. Netlist and constraint sign in checks and validation. Responsible to complete synthesis till final-opt with DFT insertion Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power...
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Lead ASIC Synthesis Expert
3 days ago
bangalore, India beBeeSynthesis Full timeSynthesis Engineer RoleThe Synthesis Engineer plays a pivotal role in the ASIC design process, particularly at sub-5nm technologies. Effective innovation at this stage can significantly enhance subsequent BackEnd execution and overall chip quality.Validate synthesis SDC qualityOptimize tool variables and methodologies to achieve optimal area/powerAnalyze...
