Advanced Semiconductor Design Engineer

1 week ago

nashik, India beBeeSenior Full time

Job Summary:We are looking for an experienced Analog Layout / IP Delivery Engineer with a strong background in designing and integrating high-speed analog IPs at the chip level. This role requires expertise in ICC2-based top-level integration, extensive IP verification experience, and the ability to run block-level simulations independently.Key Responsibilities:Analog Layout & IntegrationThe ideal candidate will lead chip-level planning and integration of high-speed analog IPs, execute complete analog layout design including floor planning, routing, device matching, shielding, EM/IR checks, and parasitic optimization, and run post-layout simulations (corners, Monte Carlo, extracted netlist) and ensure correlation with schematic.IP Verification & SignoffThe successful candidate will own the entire IP verification process: DRC, LVS, ERC, ANT, PEX, and reliability checks, ensure zero-violation GDS delivery for IP signoff, and work closely with foundry teams on PDK clarifications, rule updates, model issues, PEX discussions, and tape-out requirements.Cross-Functional CollaborationHe/she will coordinate with PD, DV, circuit design, packaging, and integration teams for seamless IP delivery, prepare and deliver comprehensive IP documentation, abstracts, verification reports, and final GDS.Process & Technology ExpertiseMandatory hands-on experience with TSMC 5nm is required, as well as a strong understanding of ICC2 flows for complete SoC/top-level integration and the ability to run extracted and post-layout simulations for designed blocks.Required Skills & Qualifications:8+ years of proven experience in Analog/Mixed-Signal Layout

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