Principal Silicon Physical Design Engineer

About usGraphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world's most transformative technologies.Job Summary We are looking for high-quality silicon physical design engineers to complement our existing exceptional team. We have a range of roles available with focus on those with extensive ranges of skills and experience although exceptional candidates with less experience will be considered. We want people who work collaboratively and proactively within a team focusing on collectively achieving our goals and creating the right engineering solutions. Good communication is essential, as is the ability to adapt and learn – we value the right characteristics more than specific experience.For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to take ownership of their designs and problem solutions. You will become part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure.The TeamThe physical design team sits within the wider silicon design team which includes RTL, verification and DFT and with whom we collaborate extensively. Our work additionally involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and then to build the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC).Responsibilities and DutiesApplicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, focusing on achieving robust, high-performance and power-efficient designs in leading-edge process technologies while meeting ambitious development schedules. Contributions are expected to span multiple areas and involve:using state-of-the-art EDA tools and in-house Graphcore flows to deliver final designs that are of sign-off qualityenhancing existing flows and in-house tools/APIs to support new features and/or methodologiesanalysis and/or debugging of complex engineering problems leading to workable solutionsdeveloping an understanding of emerging technical issues and applying that knowledge to optimise in-house flows and methodologiesCandidates will be expected to work closely both with other teams within Graphcore and with 3rd party support engineers/contractors, ensuring good communication between all parties, and to contribute meaningfully to the overall efficiency and success of the Physical Team.Candidate ProfileEssential:A Degree in Electronic/Electrical Engineering, Computer Science or related subjectBe highly motivated, a self-starter, and a team playerEnjoy taking responsibility and improving skills and knowledgeExcellent problem-solving skills for debugging issues seen and finding root causesAbility to program/script (required to solve design issues, typically in Tcl and Python)Experience in 7nm or smaller technologiesAn excellent breadth of experience with physical design flows including: Floorplanning/Budgeting, Synthesis, Place and Route, Clock CTS, Timing Analysis, Logical Equivalence, Physical Verification (DRC/LVS/ERC)Minimum 9/10 years relevant engineering experienceDesirable – knowledge/experience in most of the followingIn depth expertise in many aspects of physical design flowsStructuring of builds to maximise PPASilicon transistor knowledge including std cell libraries and/or memories2D and 3D design (CoWoS, UCIe etc.)High speed, high power and/or full reticle chip designsExperience with Ethernet, PCIe, LPDDR, HBM, UCIe implementationsPower integrity and optimization2nm or 3nm technologiesChip finishing (pad rings, chip level LVS/DRC/ERC)Design for testTeam managementTechnical leadershipProject Planning