RTL (ASIC) Design Engineer

7 days ago


bangalore, India ACL Digital Full time

RTL Design Engineer (SDC Constraints)𝗘𝘅𝗽𝗲𝗿𝗶𝗲𝗻𝗰𝗲: 𝟳+ 𝗬𝗲𝗮𝗿𝘀𝗟𝗼𝗰𝗮𝘁𝗶𝗼𝗻: 𝗕𝗮𝗻𝗴𝗮𝗹𝗼𝗿𝗲𝗪𝗼𝗿𝗸 𝗠𝗼𝗱𝗲: 𝗛𝘆𝗯𝗿𝗶𝗱 / 𝗥𝗲𝗺𝗼𝘁𝗲🔍 𝗝𝗼𝗯 𝗢𝘃𝗲𝗿𝘃𝗶𝗲𝘄We are looking for a highly skilled Senior RTL ASIC Design Engineer with strong hands-on experience in SDC Constraints. The ideal candidate will have deep expertise in RTL design, timing constraints, and close collaboration with synthesis and STA teams.🧠 𝗞𝗲𝘆 𝗥𝗲𝘀𝗽𝗼𝗻𝘀𝗶𝗯𝗶𝗹𝗶𝘁𝗶𝗲𝘀➖ Design and develop RTL (Verilog/SystemVerilog) for complex ASIC blocks and subsystems➖ Create, review, and maintain SDC constraints (clock definitions, I/O constraints, false paths, multicycle paths, exceptions, etc.)➖ Work closely with synthesis, STA, physical design, and verification teams to achieve timing closure➖ Perform RTL quality checks, linting, and CDC analysis➖ Support timing debugging and constraint optimization across multiple design iterations➖ Participate in architecture discussions and design reviews➖ Ensure deliverables meet performance, power, and area (PPA) goals.✅ 𝗠𝗮𝗻𝗱𝗮𝘁𝗼𝗿𝘆 𝗦𝗸𝗶𝗹𝗹𝘀 & 𝗘𝘅𝗽𝗲𝗿𝗶𝗲𝗻𝗰𝗲▪️ 7+ years of hands-on experience in RTL ASIC design▪️ Strong and mandatory expertise in SDC▪️ Clocking strategies▪️ Timing exceptions▪️ Constraint validation and debug▪️ Proficiency in Verilog/SystemVerilog▪️ Solid understanding of ASIC design flow (RTL → Synthesis → STA → P&R)▪️ Experience working with Synopsys tools (DC, PrimeTime – preferred)▪️ Strong knowledge of timing concepts and timing closure▪️ Excellent debugging and problem-solving skills🌟 𝗚𝗼𝗼𝗱 𝘁𝗼 𝗛𝗮𝘃𝗲🔸 Experience in low-power design techniques🔸 Exposure to CDC/RDC methodologies🔸 Experience with complex SoC designs🔸 Scripting knowledge (Tcl / Perl / Python)🔸 Prior experience working with global or distributed teams



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