Senior Digital Testing Expert

7 days ago

ghaziabad, India beBeeDft Full time

Job OverviewWe are seeking a senior digital testing expert to drive architecture, planning, and implementation of complex SoC/ASIC designs.The ideal candidate will have extensive experience in DFT for complex ASIC or SoC designs, expertise in scan insertion, compression, ATPG, MBIST, and boundary scan, and hands-on experience with DFT tools such as Synopsys, Siemens EDA, and Cadence/others.Key Responsibilities:Develop and drive DFT strategy and architecture for multiple ASIC/SoC projects.Implement and verify DFT features like:Scan insertion and compression (e.g., EDT)ATPG pattern generation and fault gradingMBIST and Logic BIST insertion and validationBoundary scan (IEEE 1149.1/1149.6), IJTAG (1687)Manage end-to-end DFT flow — from RTL to gate-level netlist and silicon bring-up.Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.Perform pattern generation, fault simulation, and debug test coverage gaps.Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.Support silicon bring-up, test vector validation on ATE, and yield optimization.Required Skills and Experience:Bachelor's degree in Electronics, Electrical, or VLSI Design.7+ years of experience in DFT for complex ASIC or SoC designs.Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.Hands-on experience with DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX, Siemens EDA: Tessent ScanPro, MBIST, IJTAG, Cadence/others: Modus, Encounter Test.Strong knowledge of RTL design, STA, and synthesis flows.Proficient in scripting languages (Python, Perl, Tcl) for flow automation.Deep understanding of silicon test challenges and test coverage improvement.Strong leadership, team collaboration, and communication skills.Benefits:Competitive salary and fast-track growth opportunities.Opportunity to collaborate with top-tier engineers and global semiconductor leaders.Why This Role?This role offers the opportunity to lead DFT for high-performance, next-gen SoCs and ASICs, driving innovation and excellence in digital testing.Interested candidates can submit their CV for consideration.

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