Microarchitect and RTL Design Engineer

5 days ago

bangalore, India Baya Systems Full time

Baya Systems is inspired by the baya bird, also known as the weaver. Baya birds weave very unique and intricate hanging nests from different materials. The nests are robust and safe while being extremely lightweight and efficient.Baya is a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era.  We focus on software-driven, unified fabric solutions for single-die and multi-die systems. We design and license disruptive intellectual property for use in semiconductor chips, with software development platforms to simplify the design process and reduce the time to market for complex System-on-Chip (SoC) and multi-chiplet systems. This enables our partners to innovate and deliver compelling solutions for data center, infrastructure, AI, Automotive, and Edge IoT markets. We are looking for energetic and dedicated individuals share our passion for enabling innovation and excellence in the semiconductor industry that empowers game-changing products and services MICROARCHITECT AND RTL DESIGN  BENGALURU, INDIAAbout the role:We are seeking a seasoned Microarchitect and RTL Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutionsResponsibilities:Design and develop microarchitectures for a set of highly configurable IP'sMicroarchitecture and RTL coding ensuring optimal performance, power, areaCollaborate with software teams to define configuration requirements, verification collaterals etc.Work with verification teams on assertions, test plans, debug, coverage etc.Qualifications and Preferred Skills:BS, MS in Electrical Engineering, Computer Engineering or Computer Science8+ years and current hands-on experience in microarchitecture and RTL developmentProficiency in Verilog, System VerilogFamiliarity with industry-standard EDA tools and methodologiesExperience with large high-speed, pipelined, stateful designs, and low power designsIn-depth understanding of on-chip interconnects and NoC'sExperience within Arm ACE/CHI or similar coherency protocolsExperience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and NoC'sFamiliarity with RAS designs, QoS in fabrics, PCIe/IO is a plusExperience with modern programming languages like Python is a plusExcellent problem-solving skills and attention to detailStrong communication and collaboration skills Compensation:Salary commensurate with experiencePerformance incentivesComprehensive medical, dental, and vision benefits401(k) retirement planEquity

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