Senior Analog Design Expert

6 days ago

Kolhapur, India beBeeAnalog Full time

Job DescriptionAs a Senior Analog Layout Engineer, you will play a key role in designing and integrating high-speed analog IPs at the chip level. This requires deep knowledge of ICC2-based top-level integration, extensive IP verification experience, and the ability to run block-level simulations independently.The ideal candidate will take full ownership of IP development, verification, integration, and delivery – including foundry coordination, signoff, and tape-out. You will be responsible for leading chip-level planning and integration of high-speed analog IPs, executing complete analog layout design, and running post-layout simulations.You will also own the entire IP verification process, ensuring zero-violation GDS delivery for IP signoff, and working closely with foundry teams on PDK clarifications, rule updates, model issues, and tape-out requirements.A strong understanding of chip-level hierarchy, integration, and physical interfaces is essential, as well as proficiency in Cadence Virtuoso, PVS, Calibre, and extraction tools. In-depth knowledge of DRC/LVS/ERC, PEX & RC Extraction, signoff decks, and reliability checks is also required.Key Responsibilities:Lead chip-level planning and integration of high-speed analog IPs.Execute complete analog layout design, including floor planning, routing, device matching, shielding, EM/IR checks, and parasitic optimization.Run post-layout simulations (corners, Monte Carlo, extracted netlist) and ensure correlation with schematic.Own the entire IP verification process: DRC, LVS, ERC, ANT, PEX, and reliability checks.Required Skills and Qualifications8+ years of proven experience in Analog/Mixed-Signal Layout.Deep expertise in high-speed IPs: SERDES, PLL, ADC/DAC, Tx/Rx, clocking blocks.Strong understanding of chip-level hierarchy, integration, and physical interfaces.Proficiency in Cadence Virtuoso, PVS, Calibre, and extraction tools.In-depth knowledge of DRC/LVS/ERC, PEX & RC Extraction, signoff decks, and reliability checks.BenefitsMandatory hands-on experience with TSMC 5nm.Experience interfacing with foundry teams for rule clarifications and tape-out signoff.Strong sense of ownership in IP development, customer communications, and documentation.OthersGood to Have: Experience with other advanced process nodes (7nm/3nm).Exposure to SERDES/PCIe/MIPI/USB high-speed IPs.

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