High-Speed Analog Design Expert

5 days ago

erode, India beBeeEngineer Full time

About the RoleWe are seeking a highly experienced Senior Analog Layout Engineer to work on high-speed analog chip development in advanced TSMC 5nm technology.Key ResponsibilitiesHandle chip-level planning and integration of high-speed analog IPsPerform complete analog layout design including floorplanning, routing, matching, shielding, EM/IR checks, and parasitic optimizationRun post-layout simulations (extracted netlist, corners, Monte Carlo) and ensure correlation with schematicStrong understanding of ICC2 flows for complete SoC/top-level integrationLead IP verification, including DRC, LVS, ERC, ANT, PEX, and reliability checksRequired Skills and Qualifications8+ years of solid experience in Analog/Mixed-Signal LayoutDeep expertise in high-speed IPs (SERDES, PLL, ADC/DAC, Tx/Rx, clocking blocks)Strong understanding of chip-level integration, hierarchy, and physical interfacesHands-on experience with ICC2 and top-level integration flowsAbility to run simulations for the blocks being designed (post-layout, extracted)Working ConditionsRemote / India (must support USA/Canada time zone)Willing to travel to the U.S. for project release (as required)

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